Re: [uCsimm] cs8900 & wait-states

From: daniel haensse (daniel.haensse@fhk.usz.ch)
Date: Thu Dec 07 2000 - 02:01:52 EST


Am Don, 07 Dez 2000 schrieben Sie:
> sticke_m wrote:
> >
> > On Wed, 6 Dec 2000, Jason Harris wrote:
> >
> > >
> > > >There's another possibility to improve speed for the first hardware release with
> > > >software byte swapping: Instead of the rol.w instructions, simple byte moves
> > > >will improve the block transfer speed by ~30%.
> > >
> > > Not sure I understand this. The 16 bit interface to the CS8900A is byte reversed in
> > > hardware (examine the schematic). This means that the commands sent to the device
> > > have to be byte reversed wrt the values in the data sheet, but when it comes to
> > > receiving and transmitting packet buffers we can do 16bit reads and writes without
> > > worrying about byte ordering. So- How do you get a 30% improvement in packet transfer
> > > times?
> >
> > My idea is.
> > The CS8900 has been made for an ISA-bus (Intel)that has another byte order
> > than the 68000 and if you swap them you can access the registers as shown
> > in the data-sheets. It's the only reason I can find for that.
> >
>
> You almost have it right... Hardware byte swapping is specifically
> called for in the CS8900 manual when interfacing it to a Motorola 68K
> processor. It is simply the way it was designed to be used.
>
>
> TomW

What is the historical reason for this byte ordering confusion? Some patents
from intel?

Dani
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