I've found that a lot of recent PC motherboard chipsets
and notebook chipsets do not use a stable clock source.
The cheap thing to use is the ISA BCLK signal, which is
interesting in that it is unrelated to the bus timing.
Like the national grid, the total number of clock edges
on BCLK is correct over time, but the short term phase and
frequency can slew around by large amounts. I've observed
ISA slots changing between 1MHz and 20MHz for short times.
It's actually great for 19200 baud, or serial mice, or
external modems that are doing network connections (where
the PPP protocol does its own invisible error correction).
Sadly, the ISA bus clock is about 70 times the bit rate
at 115kbaud, which is nasty since most UARTs want to have
16 times oversampling of the receive data if they can get it.
One one chipset, I noticed that it was alternating between
64 and 80 as the divisor, to get the correct long term average,
so that transmit bits looked distinctly unusual.
I've also seen very weak line drivers that cannot manage
more than 6ft of cable at full speed without sagging down.
Combine these effects, and you can get eye diagrams
(timing with respect to start bit leading edge) where
you're really wondering how the data is getting through.
The brute force fix, for a development workstation, is
to levelshift the signals back to TTL on the back of the
PC, apply a NRZ style retiming to the bits, and then
hand them on to the ucsimm.
I took the simpler approach, of finding an old computer
that has a 'decent' serial port implementation and using
that to control the RS232 port on the ucsimm. I just
telnet from my development station to that machine,
then use minicom from there to download to the ucsimm.
I've noticed some Windows computers are shipped with the
serial port interrupts disabled (usually in the BIOS).
This makes sense on a platform with lots of multimedia
stuff, poor OS support for sharing interrupts and a
severe shortage of interrupt lines to allocate around.
Polled RS232 doesn't work very well above 9600 baud!
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