Re: [uCsimm] For exact date

From: 권석근 (kwonsk@mutech.co.kr)
Date: Thu Mar 09 2000 - 04:12:34 EST


Hi, Vladimir

And another reason for my assumption aoubt CLK32 = 32.768KHz
In PLL Block Diagram (fig. 5-1 again)
VCO = PLL multiplier (506) * 32.768KHz = 16.580608MHz.
This calulation result (at the page 5-2) means CLK32=32.768KHz

Thanks.
kwonsk.

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