diff -r -u binutils-2.10-orig/bfd/archures.c binutils-2.10/bfd/archures.c --- binutils-2.10-orig/bfd/archures.c Thu May 10 07:58:03 2001 +++ binutils-2.10/bfd/archures.c Thu Jun 14 13:16:35 2001 @@ -79,6 +79,7 @@ .#define bfd_mach_m68040 6 .#define bfd_mach_m68060 7 .#define bfd_mach_cpu32 8 +.#define bfd_mach_mcf5200 9 . bfd_arch_vax, {* DEC Vax *} . bfd_arch_i960, {* Intel 960 *} . {* The order of the following is important. diff -r -u binutils-2.10-orig/bfd/bfd-in2.h binutils-2.10/bfd/bfd-in2.h --- binutils-2.10-orig/bfd/bfd-in2.h Thu May 10 07:58:03 2001 +++ binutils-2.10/bfd/bfd-in2.h Thu Jun 14 13:16:36 2001 @@ -1295,6 +1295,7 @@ #define bfd_mach_m68040 6 #define bfd_mach_m68060 7 #define bfd_mach_cpu32 8 +#define bfd_mach_mcf5200 9 bfd_arch_vax, /* DEC Vax */ bfd_arch_i960, /* Intel 960 */ /* The order of the following is important. diff -r -u binutils-2.10-orig/bfd/cpu-m68k.c binutils-2.10/bfd/cpu-m68k.c --- binutils-2.10-orig/bfd/cpu-m68k.c Thu May 10 07:58:04 2001 +++ binutils-2.10/bfd/cpu-m68k.c Thu Jun 14 13:16:36 2001 @@ -28,14 +28,15 @@ static const bfd_arch_info_type arch_info_struct[] = { - N(bfd_mach_m68000, "m68k:68000", false, &arch_info_struct[1]), - N(bfd_mach_m68008, "m68k:68008", false, &arch_info_struct[2]), - N(bfd_mach_m68010, "m68k:68010", false, &arch_info_struct[3]), - N(bfd_mach_m68020, "m68k:68020", false, &arch_info_struct[4]), - N(bfd_mach_m68030, "m68k:68030", false, &arch_info_struct[5]), - N(bfd_mach_m68040, "m68k:68040", false, &arch_info_struct[6]), - N(bfd_mach_cpu32, "m68k:cpu32", false, &arch_info_struct[7]), - N(bfd_mach_m68060, "m68k:68060", false, 0), + N(bfd_mach_m68000, "m68k:68000", false, &arch_info_struct[1]), + N(bfd_mach_m68008, "m68k:68008", false, &arch_info_struct[2]), + N(bfd_mach_m68010, "m68k:68010", false, &arch_info_struct[3]), + N(bfd_mach_m68020, "m68k:68020", false, &arch_info_struct[4]), + N(bfd_mach_m68030, "m68k:68030", false, &arch_info_struct[5]), + N(bfd_mach_m68040, "m68k:68040", false, &arch_info_struct[6]), + N(bfd_mach_cpu32, "m68k:cpu32", false, &arch_info_struct[7]), + N(bfd_mach_mcf5200, "m68k:5200", false, &arch_info_struct[8]), + N(bfd_mach_m68060, "m68k:68060", false, 0), }; const bfd_arch_info_type bfd_m68k_arch = diff -r -u binutils-2.10-orig/gas/config/tc-m68k.c binutils-2.10/gas/config/tc-m68k.c --- binutils-2.10-orig/gas/config/tc-m68k.c Thu May 10 07:58:09 2001 +++ binutils-2.10/gas/config/tc-m68k.c Thu Jun 14 13:16:36 2001 @@ -72,6 +72,12 @@ to denote pic relocations. */ int flag_want_pic; +/* This option disables the conversion of short PC relative branches into + longer absolute branches. This allows for generation of PIC code which + can utilise the jbsr, jbra pseudo op codes (which saves about 5% code + size in our environment) */ +static int m68k_relative_branches; + static int flag_short_refs; /* -l option */ static int flag_long_jumps; /* -S option */ @@ -396,8 +402,8 @@ { m68881, "68881", 0 }, { m68851, "68851", 0 }, { mcf5200, "5200", 0 }, - { mcf5206e, "5206e", 0 }, - { mcf5307, "5307", 0}, + { mcfmac, "mac", 0 }, + { mcfhwdiv, "hwdiv", 0 }, /* Aliases (effectively, so far as gas is concerned) for the above cpus. */ { m68020, "68k", 1 }, @@ -425,9 +431,11 @@ { cpu32, "68349", 1 }, { cpu32, "68360", 1 }, { m68881, "68882", 1 }, - { mcf5200, "5202", 1 }, - { mcf5200, "5204", 1 }, - { mcf5200, "5206", 1 }, + { mcf5200, "5202", 1 }, + { mcf5200, "5204", 1 }, + { mcf5200, "5206", 1 }, + { mcf5200|mcfhwdiv|mcfmac, "5206e", 1 }, + { mcf5200|mcfhwdiv|mcfmac, "5307", 1 } }; static const int n_archs = sizeof (archs) / sizeof (archs[0]); @@ -634,11 +642,15 @@ */ if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */ { + if (m68k_relative_branches) + as_fatal(_("Tried to convert PC relative branch to absolute jump")); opcode[0] = 0x4e; opcode[1] = 0xf9; } else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */ { + if (m68k_relative_branches) + as_fatal(_("Tried to convert PC relative BSR to absolute JSR")); opcode[0] = 0x4e; opcode[1] = 0xb9; } @@ -3474,7 +3486,7 @@ insert_reg (init_table[i].name, init_table[i].number); } -static int no_68851, no_68881; +static int no_68851, no_68881, no_mac, no_hwdiv; #ifdef OBJ_AOUT /* a.out machine type. Default to 68020. */ @@ -3899,8 +3911,6 @@ control_regs = cpu32_control_regs; break; case mcf5200: - case mcf5206e: - case mcf5307: control_regs = mcf_control_regs; break; default: @@ -3959,6 +3969,30 @@ if (no_68851 && (current_architecture & m68851)) as_bad (_("options for 68851 and no-68851 both given")); + /* Check for basic ColdFire MAC and hwdiv validity */ + if (no_mac && (current_architecture & mcfmac)) + as_bad ("options for ColdFire mac and no-mac both given"); + if (no_hwdiv && (current_architecture & mcfhwdiv)) + as_bad ("options for ColdFire hwdiv and no-hwdiv both given"); + + /* Make sure that we have a ColdFire for the MAC or HWDIV options */ + if (current_architecture & mcfmac) + { + if ( !arch_coldfire_p (current_architecture) ) + { + as_bad ("mac specified with a non-ColdFire architecture"); + } + } + + if (current_architecture & mcfhwdiv) + { + if ( !arch_coldfire_p (current_architecture) ) + { + as_bad ("hwdiv specified with a non-ColdFire architecture"); + } + } + + #ifdef OBJ_AOUT /* Work out the magic number. This isn't very general. */ if (current_architecture & m68000) @@ -4322,6 +4356,8 @@ if (fragP->fr_opcode[0] == 0x61) /* BSR */ { + if (m68k_relative_branches) + as_fatal(_("Tried to convert PC relative BSR to absolute JSR")); fragP->fr_opcode[0] = 0x4E; fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */ @@ -4339,6 +4375,8 @@ /* BRA */ else if (fragP->fr_opcode[0] == 0x60) { + if (m68k_relative_branches) + as_fatal(_("Tried to convert PC relative branch to absolute jump")); fragP->fr_opcode[0] = 0x4E; fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, @@ -4361,6 +4399,8 @@ } break; case TAB (BCC68000, LONG): + if (m68k_relative_branches) + as_fatal(_("Tried to convert PC relative conditional branch to absolute jump")); /* only Bcc 68000 instructions can come here */ /* change bcc into b!cc/jmp absl long */ fragP->fr_opcode[0] ^= 0x01; /* invert bcc */ @@ -4381,6 +4421,8 @@ /* only DBcc 68000 instructions can come here */ /* change dbcc into dbcc/jmp absl long */ /* JF: these used to be fr_opcode[2-7], but that's wrong */ + if (m68k_relative_branches) + as_fatal(_("Tried to convert DBcc to absolute jump")); *buffer_address++ = 0x00; /* branch offset = 4 */ *buffer_address++ = 0x04; *buffer_address++ = 0x60; /* put in bra pc+6 */ @@ -4546,6 +4588,8 @@ /* FIXME, we should check abs val, pick short or long */ if (fragP->fr_opcode[0] == 0x61) { + if (m68k_relative_branches) + as_fatal(_("Tried to convert PC relative BSR to absolute JSR")); fragP->fr_opcode[0] = 0x4E; fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */ fix_new (fragP, fragP->fr_fix, 4, @@ -4555,6 +4599,8 @@ } else if (fragP->fr_opcode[0] == 0x60) { + if (m68k_relative_branches) + as_fatal(_("Tried to convert PC relative branch to absolute jump")); fragP->fr_opcode[0] = 0x4E; fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */ fix_new (fragP, fragP->fr_fix, 4, @@ -4639,6 +4685,8 @@ } else { + if (m68k_relative_branches) + as_fatal(_("Tried to convert PC relative conditional branch to absolute jump")); /* change bcc into b!cc/jmp absl long */ fragP->fr_opcode[0] ^= 0x01; /* invert bcc */ fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */ @@ -4675,6 +4723,8 @@ } else { + if (m68k_relative_branches) + as_fatal(_("Tried to convert DBcc to absolute jump")); /* change dbcc into dbcc/jmp absl long */ /* JF: these used to be fr_opcode[2-4], which is wrong. */ buffer_address[0] = 0x00; /* branch offset = 4 */ @@ -4860,6 +4910,8 @@ if (!HAVE_LONG_BRANCH(current_architecture)) { + if (m68k_relative_branches) + as_fatal(_("Tried to convert PC relative branch to absolute jump")); offset = to_addr - S_GET_VALUE (to_symbol); md_number_to_chars (ptr, (valueT) 0x4EF9, 2); md_number_to_chars (ptr + 2, (valueT) offset, 4); @@ -6773,6 +6825,8 @@ {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16}, #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6) {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32}, +#define OPTION_RELATIVE_BRANCHES (OPTION_MD_BASE + 7) + {"pcrel", no_argument, NULL, OPTION_RELATIVE_BRANCHES}, {NULL, no_argument, NULL, 0} }; size_t md_longopts_size = sizeof(md_longopts); @@ -6807,7 +6861,7 @@ const char *oarg = arg; arg += 3; - if (*arg == 'm') + if ((arg[0] == 'm') && (arg[1] != 'a')) { arg++; if (arg[0] == 'c' && arg[1] == '6') @@ -6827,6 +6881,10 @@ no_68881 = 1; else if (arch == m68851) no_68851 = 1; + else if (arch == mcfmac) + no_mac = 1; + else if (arch == mcfhwdiv) + no_hwdiv = 1; else goto unknown; } @@ -6857,6 +6915,16 @@ current_architecture |= m68851; no_68851 = 0; } + else if (arch == mcfmac) + { + current_architecture |= mcfmac; + no_mac = 0; + } + else if (arch == mcfhwdiv) + { + current_architecture |= mcfhwdiv; + no_hwdiv = 0; + } else /* ??? */ abort (); @@ -6923,6 +6991,10 @@ m68k_rel32_from_cmdline = 1; break; + case OPTION_RELATIVE_BRANCHES: + m68k_relative_branches = 1; + break; + default: return 0; } @@ -6938,8 +7010,8 @@ 680X0 options:\n\ -l use 1 word for refs to undefined symbols [default 2]\n\ -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\ - | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\ - | -mcpu32 | -m5200\n\ + | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32\n\ + | -m5200 | -m5202 | -m5203 | -m5204 | -m5206 | -m5206e | -m5307\n\ specify variant of 680X0 architecture [default 68020]\n\ -m68881 | -m68882 | -mno-68881 | -mno-68882\n\ target has/lacks floating-point coprocessor\n\ @@ -6948,6 +7020,12 @@ -m68851 | -mno-68851\n\ target has/lacks memory-management unit coprocessor\n\ [default yes for 68020 and up]\n\ +-mmac | -mno-mac\n\ + target has/lacks ColdFire MAC unit\n\ + [default yes for 5206e and 5307]\n\ +-mhwdiv | -mno-hwdiv\n\ + target has/lacks ColdFire Hardware Divide unit\n\ + [default yes for 5206e and 5307]\n\ -pic, -k generate position independent code\n\ -S turn jbsr into jsr\n\ --register-prefix-optional\n\ @@ -6957,7 +7035,9 @@ --base-size-default-16 base reg without size is 16 bits\n\ --base-size-default-32 base reg without size is 32 bits (default)\n\ --disp-size-default-16 displacement with unknown size is 16 bits\n\ ---disp-size-default-32 displacement with unknown size is 32 bits (default)\n")); +--disp-size-default-32 displacement with unknown size is 32 bits (default)\n\ +--pcrel do not turn short relative branches into long\n\ + absolute one\n")); } #ifdef TEST2 Only in binutils-2.10/gas/config: tc-m68k.c~ diff -r -u binutils-2.10-orig/gas/doc/as.texinfo binutils-2.10/gas/doc/as.texinfo --- binutils-2.10-orig/gas/doc/as.texinfo Thu May 10 07:58:13 2001 +++ binutils-2.10/gas/doc/as.texinfo Thu Jun 14 13:16:36 2001 @@ -497,7 +497,8 @@ Shorten references to undefined symbols, to one word instead of two. @item -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 -@itemx | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -mcpu32 | -m5200 +@itemx | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -mcpu32 +@itemx | -m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m5307 Specify what processor in the 68000 family is the target. The default is normally the 68020, but this can be changed at configuration time. @@ -511,6 +512,16 @@ @item -m68851 | -mno-68851 The target machine does (or does not) have a memory-management unit coprocessor. The default is to assume an MMU for 68020 and up. + +@item -mmac | -mno-mac +The target machine does (or does not) have a ColdFire Multiply and +ACcumulate unit. The default is to assume a MAC unit on the 5206e +and 5307 processors. This option is only valid for ColdFire targets. + +@item -mhwdiv | -mno-hwdiv +The target machine does (or does not) have a ColdFire hardware divide +unit. The default is to assume divide instructions exist on the 5206e +and 5307 processors. This option is only valid for ColdFire targets. @end table @end ifset diff -r -u binutils-2.10-orig/gas/doc/c-m68k.texi binutils-2.10/gas/doc/c-m68k.texi --- binutils-2.10-orig/gas/doc/c-m68k.texi Thu May 10 07:58:13 2001 +++ binutils-2.10/gas/doc/c-m68k.texi Thu Jun 14 13:16:36 2001 @@ -144,6 +144,11 @@ Assemble for the CPU32 family of chips. @item -m5200 +@itemx -m5202 +@itemx -m5204 +@itemx -m5206 +@itemx -m5206e +@itemx -m5307 Assemble for the ColdFire family of chips. @item -m68881 @@ -167,6 +172,24 @@ Do not assemble 68851 MMU instructions. This is the default for the 68000, 68010, and the CPU32. The 68040 accepts a somewhat different set of MMU instructions. + +@item -mmac +Assemble ColdFire MAC instructions. This is the default for the 5206e +and 5307. This option is only available on ColdFire processors with a +Multiply and ACcumulate unit. + +@item -mno-mac +Do not assemble ColdFire MAC instructions. This is the default for +the 5200, 5202, 5204 and 5206. + +@item -mhwdiv +Assemble ColdFire divide instructions. This is the default for the 5206e +and 5307. This option is only available on ColdFire processors with a +hardware divide unit. + +@item -mno-hwdiv +Do not assemble ColdFire divide instructions. This is the default for +the 5200, 5202, 5204 and 5206. @end table @node M68K-Syntax diff -r -u binutils-2.10-orig/gas/testsuite/gas/m68k/all.exp binutils-2.10/gas/testsuite/gas/m68k/all.exp --- binutils-2.10-orig/gas/testsuite/gas/m68k/all.exp Thu May 10 07:58:15 2001 +++ binutils-2.10/gas/testsuite/gas/m68k/all.exp Thu Jun 14 13:16:36 2001 @@ -19,6 +19,8 @@ run_dump_test bitfield run_dump_test link run_dump_test fmoveml + run_dump_test mcf-hwdiv + run_dump_test mcf-mac set testname "68000 operands" gas_run "operands.s" "-m68000" "2>err.out" Only in binutils-2.10/gas/testsuite/gas/m68k: mcf-hwdiv.d Only in binutils-2.10/gas/testsuite/gas/m68k: mcf-hwdiv.s Only in binutils-2.10/gas/testsuite/gas/m68k: mcf-mac.d Only in binutils-2.10/gas/testsuite/gas/m68k: mcf-mac.s diff -r -u binutils-2.10-orig/include/opcode/m68k.h binutils-2.10/include/opcode/m68k.h --- binutils-2.10-orig/include/opcode/m68k.h Thu May 10 07:58:20 2001 +++ binutils-2.10/include/opcode/m68k.h Thu Jun 14 13:16:36 2001 @@ -35,9 +35,9 @@ #define m68882 m68881 /* synonym for -m68881. otherwise unused. */ #define m68851 0x080 #define cpu32 0x100 /* e.g., 68332 */ -#define mcf5200 0x200 -#define mcf5206e 0x400 -#define mcf5307 0x800 +#define mcf5200 0x0200 +#define mcfmac 0x0400 /* Any V2+ core can have a MAC unit bolted on */ +#define mcfhwdiv 0x0800 /* Likewise for a hardware divide unit */ /* handy aliases */ #define m68040up (m68040 | m68060) @@ -45,7 +45,7 @@ #define m68020up (m68020 | m68030up) #define m68010up (m68010 | cpu32 | m68020up) #define m68000up (m68000 | m68010up) -#define mcf (mcf5200 | mcf5206e | mcf5307) +#define mcf (mcf5200) #define mfloat (m68881 | m68882 | m68040 | m68060) #define mmmu (m68851 | m68030 | m68040 | m68060) diff -r -u binutils-2.10-orig/opcodes/m68k-dis.c binutils-2.10/opcodes/m68k-dis.c --- binutils-2.10-orig/opcodes/m68k-dis.c Thu May 10 07:58:23 2001 +++ binutils-2.10/opcodes/m68k-dis.c Thu Jun 14 13:16:36 2001 @@ -254,9 +254,12 @@ case bfd_mach_m68060: arch_mask = m68060; break; + case bfd_mach_mcf5200: + arch_mask = mcf5200; + break; } - arch_mask |= m68881 | m68851; + arch_mask |= m68881 | m68851 | mcfmac | mcfhwdiv; bestmask = 0; FETCH_DATA (info, buffer + 2); diff -r -u binutils-2.10-orig/opcodes/m68k-opc.c binutils-2.10/opcodes/m68k-opc.c --- binutils-2.10-orig/opcodes/m68k-opc.c Thu May 10 07:58:23 2001 +++ binutils-2.10/opcodes/m68k-opc.c Thu Jun 14 13:16:36 2001 @@ -242,7 +242,7 @@ {"cpusha", one(0xf420|SCOPE_ALL), one(0xff38), "ce", m68040up }, {"cpushl", one(0xf420|SCOPE_LINE), one(0xff38), "ceas", m68040up }, -{"cpushl", one(0x04e8), one(0xfff8), "as", mcf }, +{"cpushl", one(0xf4e8), one(0xfff8), "as", mcf }, {"cpushp", one(0xf420|SCOPE_PAGE), one(0xff38), "ceas", m68040up }, #undef SCOPE_LINE @@ -300,22 +300,20 @@ {"dbvc", one(0054310), one(0177770), "DsBw", m68000up }, {"dbvs", one(0054710), one(0177770), "DsBw", m68000up }, -{"divsw", one(0100700), one(0170700), ";wDd", m68000up }, -{"divsw", one(0100700), one(0170700), "vsDd", mcf5307 | mcf5206e }, +{"divsw", one(0100700), one(0170700), ";wDd", m68000up | mcfhwdiv }, {"divsl", two(0046100,0006000),two(0177700,0107770),";lD3D1", m68020up|cpu32 }, {"divsl", two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 }, -{"divsl", two(0046100,0004000),two(0177700,0107770),"vsDD", mcf5307 | mcf5206e }, +{"divsl", two(0046100,0004000),two(0177700,0107770),"vsDD", mcfhwdiv }, {"divsll", two(0046100,0004000),two(0177700,0107770),";lD3D1",m68020up|cpu32 }, {"divsll", two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 }, -{"divuw", one(0100300), one(0170700), ";wDd", m68000up }, -{"divuw", one(0100300), one(0170700), "vsDd", mcf5307 | mcf5206e }, +{"divuw", one(0100300), one(0170700), ";wDd", m68000up | mcfhwdiv }, {"divul", two(0046100,0002000),two(0177700,0107770),";lD3D1", m68020up|cpu32 }, {"divul", two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 }, -{"divul", two(0046100,0000000),two(0177700,0107770),"vsDD", mcf5307 | mcf5206e }, +{"divul", two(0046100,0000000),two(0177700,0107770),"vsDD", mcfhwdiv }, {"divull", two(0046100,0000000),two(0177700,0107770),";lD3D1",m68020up|cpu32 }, {"divull", two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 }, @@ -1242,43 +1240,43 @@ {"lsrl", one(0160250), one(0170770), "DdDs", m68000up | mcf }, /* FIXME: add MAM mode (`&' after operand) / remove MACM */ -{"macw", two(0120000, 0000000), two(0170660, 0005400), "uMum", mcf5307 | mcf5206e }, -{"macw", two(0120000, 0001000), two(0170660, 0005400), "uMumMh", mcf5307 | mcf5206e }, -{"macw", two(0120220, 0000000), two(0170670, 0005460), "uNuoasRn", mcf5307 | mcf5206e }, -{"macw", two(0120230, 0000000), two(0170670, 0005460), "uNuo+sRn", mcf5307 | mcf5206e }, -{"macw", two(0120240, 0000000), two(0170670, 0005460), "uNuo-sRn", mcf5307 | mcf5206e }, -{"macw", two(0120250, 0000000), two(0170670, 0005460), "uNuodsRn", mcf5307 | mcf5206e }, -{"macw", two(0120220, 0001000), two(0170670, 0005460), "uNuoMhasRn", mcf5307 | mcf5206e }, -{"macw", two(0120230, 0001000), two(0170670, 0005460), "uNuoMh+sRn", mcf5307 | mcf5206e }, -{"macw", two(0120240, 0001000), two(0170670, 0005460), "uNuoMh-sRn", mcf5307 | mcf5206e }, -{"macw", two(0120250, 0001000), two(0170670, 0005460), "uNuoMhdsRn", mcf5307 | mcf5206e }, -{"macmw", two(0120220, 0000040), two(0170670, 0005460), "uNuoasRn", mcf5307 | mcf5206e }, -{"macmw", two(0120230, 0000040), two(0170670, 0005460), "uNuo+sRn", mcf5307 | mcf5206e }, -{"macmw", two(0120240, 0000040), two(0170670, 0005460), "uNuo-sRn", mcf5307 | mcf5206e }, -{"macmw", two(0120250, 0000040), two(0170670, 0005460), "uNuodsRn", mcf5307 | mcf5206e }, -{"macmw", two(0120220, 0001040), two(0170670, 0005460), "uNuoMhasRn", mcf5307 | mcf5206e }, -{"macmw", two(0120230, 0001040), two(0170670, 0005460), "uNuoMh+sRn", mcf5307 | mcf5206e }, -{"macmw", two(0120240, 0001040), two(0170670, 0005460), "uNuoMh-sRn", mcf5307 | mcf5206e }, -{"macmw", two(0120250, 0001040), two(0170670, 0005460), "uNuoMhdsRn", mcf5307 | mcf5206e }, - -{"macl", two(0120000, 0004000), two(0170660, 0005400), "RsRm", mcf5307 | mcf5206e }, -{"macl", two(0120000, 0005000), two(0170660, 0005400), "RsRmMh", mcf5307 | mcf5206e }, -{"macl", two(0120220, 0004000), two(0170670, 0005460), "R3R1asRn", mcf5307 | mcf5206e }, -{"macl", two(0120230, 0004000), two(0170670, 0005460), "R3R1+sRn", mcf5307 | mcf5206e }, -{"macl", two(0120240, 0004000), two(0170670, 0005460), "R3R1-sRn", mcf5307 | mcf5206e }, -{"macl", two(0120250, 0004000), two(0170670, 0005460), "R3R1dsRn", mcf5307 | mcf5206e }, -{"macl", two(0120220, 0005000), two(0170670, 0005460), "R3R1MhasRn", mcf5307 | mcf5206e }, -{"macl", two(0120230, 0005000), two(0170670, 0005460), "R3R1Mh+sRn", mcf5307 | mcf5206e }, -{"macl", two(0120240, 0005000), two(0170670, 0005460), "R3R1Mh-sRn", mcf5307 | mcf5206e }, -{"macl", two(0120250, 0005000), two(0170670, 0005460), "R3R1MhdsRn", mcf5307 | mcf5206e }, -{"macml", two(0120220, 0004040), two(0170670, 0005460), "R3R1asRn", mcf5307 | mcf5206e }, -{"macml", two(0120230, 0004040), two(0170670, 0005460), "R3R1+sRn", mcf5307 | mcf5206e }, -{"macml", two(0120240, 0004040), two(0170670, 0005460), "R3R1-sRn", mcf5307 | mcf5206e }, -{"macml", two(0120250, 0004040), two(0170670, 0005460), "R3R1dsRn", mcf5307 | mcf5206e }, -{"macml", two(0120220, 0005040), two(0170670, 0005460), "R3R1MhasRn", mcf5307 | mcf5206e }, -{"macml", two(0120230, 0005040), two(0170670, 0005460), "R3R1Mh+sRn", mcf5307 | mcf5206e }, -{"macml", two(0120240, 0005040), two(0170670, 0005460), "R3R1Mh-sRn", mcf5307 | mcf5206e }, -{"macml", two(0120250, 0005040), two(0170670, 0005460), "R3R1MhdsRn", mcf5307 | mcf5206e }, +{"macw", two(0120000, 0000000), two(0170660, 0005400), "uMum", mcfmac }, +{"macw", two(0120000, 0001000), two(0170660, 0005400), "uMumMh", mcfmac }, +{"macw", two(0120220, 0000000), two(0170670, 0005460), "uNuoasRn", mcfmac }, +{"macw", two(0120230, 0000000), two(0170670, 0005460), "uNuo+sRn", mcfmac }, +{"macw", two(0120240, 0000000), two(0170670, 0005460), "uNuo-sRn", mcfmac }, +{"macw", two(0120250, 0000000), two(0170670, 0005460), "uNuodsRn", mcfmac }, +{"macw", two(0120220, 0001000), two(0170670, 0005460), "uNuoMhasRn", mcfmac }, +{"macw", two(0120230, 0001000), two(0170670, 0005460), "uNuoMh+sRn", mcfmac }, +{"macw", two(0120240, 0001000), two(0170670, 0005460), "uNuoMh-sRn", mcfmac }, +{"macw", two(0120250, 0001000), two(0170670, 0005460), "uNuoMhdsRn", mcfmac }, +{"macmw", two(0120220, 0000040), two(0170670, 0005460), "uNuoasRn", mcfmac }, +{"macmw", two(0120230, 0000040), two(0170670, 0005460), "uNuo+sRn", mcfmac }, +{"macmw", two(0120240, 0000040), two(0170670, 0005460), "uNuo-sRn", mcfmac }, +{"macmw", two(0120250, 0000040), two(0170670, 0005460), "uNuodsRn", mcfmac }, +{"macmw", two(0120220, 0001040), two(0170670, 0005460), "uNuoMhasRn", mcfmac }, +{"macmw", two(0120230, 0001040), two(0170670, 0005460), "uNuoMh+sRn", mcfmac }, +{"macmw", two(0120240, 0001040), two(0170670, 0005460), "uNuoMh-sRn", mcfmac }, +{"macmw", two(0120250, 0001040), two(0170670, 0005460), "uNuoMhdsRn", mcfmac }, + +{"macl", two(0120000, 0004000), two(0170660, 0005400), "RsRm", mcfmac }, +{"macl", two(0120000, 0005000), two(0170660, 0005400), "RsRmMh", mcfmac }, +{"macl", two(0120220, 0004000), two(0170670, 0005460), "R3R1asRn", mcfmac }, +{"macl", two(0120230, 0004000), two(0170670, 0005460), "R3R1+sRn", mcfmac }, +{"macl", two(0120240, 0004000), two(0170670, 0005460), "R3R1-sRn", mcfmac }, +{"macl", two(0120250, 0004000), two(0170670, 0005460), "R3R1dsRn", mcfmac }, +{"macl", two(0120220, 0005000), two(0170670, 0005460), "R3R1MhasRn", mcfmac }, +{"macl", two(0120230, 0005000), two(0170670, 0005460), "R3R1Mh+sRn", mcfmac }, +{"macl", two(0120240, 0005000), two(0170670, 0005460), "R3R1Mh-sRn", mcfmac }, +{"macl", two(0120250, 0005000), two(0170670, 0005460), "R3R1MhdsRn", mcfmac }, +{"macml", two(0120220, 0004040), two(0170670, 0005460), "R3R1asRn", mcfmac }, +{"macml", two(0120230, 0004040), two(0170670, 0005460), "R3R1+sRn", mcfmac }, +{"macml", two(0120240, 0004040), two(0170670, 0005460), "R3R1-sRn", mcfmac }, +{"macml", two(0120250, 0004040), two(0170670, 0005460), "R3R1dsRn", mcfmac }, +{"macml", two(0120220, 0005040), two(0170670, 0005460), "R3R1MhasRn", mcfmac }, +{"macml", two(0120230, 0005040), two(0170670, 0005460), "R3R1Mh+sRn", mcfmac }, +{"macml", two(0120240, 0005040), two(0170670, 0005460), "R3R1Mh-sRn", mcfmac }, +{"macml", two(0120250, 0005040), two(0170670, 0005460), "R3R1MhdsRn", mcfmac }, /* NOTE: The mcf5200 family programmer's reference manual does not indicate the byte form of the movea instruction is invalid (as it @@ -1361,16 +1359,16 @@ {"movel", one(0020000), one(0170000), "olmd", mcf }, {"movel", one(0047140), one(0177770), "AsUd", m68000up }, {"movel", one(0047150), one(0177770), "UdAs", m68000up }, -{"movel", one(0120600), one(0177760), "EsRs", mcf5307 | mcf5206e }, -{"movel", one(0120400), one(0177760), "RsEs", mcf5307 | mcf5206e }, -{"movel", one(0120474), one(0177777), "#lEs", mcf5307 | mcf5206e }, -{"movel", one(0124600), one(0177760), "GsRs", mcf5307 | mcf5206e }, -{"movel", one(0124400), one(0177760), "RsGs", mcf5307 | mcf5206e }, -{"movel", one(0124474), one(0177777), "#lGs", mcf5307 | mcf5206e }, -{"movel", one(0126600), one(0177760), "HsRs", mcf5307 | mcf5206e }, -{"movel", one(0126400), one(0177760), "RsHs", mcf5307 | mcf5206e }, -{"movel", one(0126474), one(0177777), "#lHs", mcf5307 | mcf5206e }, -{"movel", one(0124700), one(0177777), "GsCs", mcf5307 | mcf5206e }, +{"movel", one(0120600), one(0177760), "EsRs", mcfmac }, +{"movel", one(0120400), one(0177760), "RsEs", mcfmac }, +{"movel", one(0120474), one(0177777), "#lEs", mcfmac }, +{"movel", one(0124600), one(0177760), "GsRs", mcfmac }, +{"movel", one(0124400), one(0177760), "RsGs", mcfmac }, +{"movel", one(0124474), one(0177777), "#lGs", mcfmac }, +{"movel", one(0126600), one(0177760), "HsRs", mcfmac }, +{"movel", one(0126400), one(0177760), "RsHs", mcfmac }, +{"movel", one(0126474), one(0177777), "#lHs", mcfmac }, +{"movel", one(0124700), one(0177777), "GsCs", mcfmac }, {"move", one(0030000), one(0170000), "*w%d", m68000up }, {"move", one(0030000), one(0170000), "ms%d", mcf }, @@ -1404,43 +1402,43 @@ {"move16", one(0xf618), one(0xfff8), "_Las", m68040up }, /* FIXME: add MAM mode (`&' after operand) / remove MSACM */ -{"msacw", two(0120000, 0000400), two(0170660, 0005400), "uMum", mcf5307 | mcf5206e }, -{"msacw", two(0120000, 0001400), two(0170660, 0005400), "uMumMh", mcf5307 | mcf5206e }, -{"msacw", two(0120220, 0000400), two(0170670, 0005460), "uNuoasRn", mcf5307 | mcf5206e }, -{"msacw", two(0120230, 0000400), two(0170670, 0005460), "uNuo+sRn", mcf5307 | mcf5206e }, -{"msacw", two(0120240, 0000400), two(0170670, 0005460), "uNuo-sRn", mcf5307 | mcf5206e }, -{"msacw", two(0120250, 0000400), two(0170670, 0005460), "uNuodsRn", mcf5307 | mcf5206e }, -{"msacw", two(0120220, 0001400), two(0170670, 0005460), "uNuoMhasRn", mcf5307 | mcf5206e }, -{"msacw", two(0120230, 0001400), two(0170670, 0005460), "uNuoMh+sRn", mcf5307 | mcf5206e }, -{"msacw", two(0120240, 0001400), two(0170670, 0005460), "uNuoMh-sRn", mcf5307 | mcf5206e }, -{"msacw", two(0120250, 0001400), two(0170670, 0005460), "uNuoMhdsRn", mcf5307 | mcf5206e }, -{"msacmw", two(0120220, 0000440), two(0170670, 0005460), "uNuoasRn", mcf5307 | mcf5206e }, -{"msacmw", two(0120230, 0000440), two(0170670, 0005460), "uNuo+sRn", mcf5307 | mcf5206e }, -{"msacmw", two(0120240, 0000440), two(0170670, 0005460), "uNuo-sRn", mcf5307 | mcf5206e }, -{"msacmw", two(0120250, 0000440), two(0170670, 0005460), "uNuodsRn", mcf5307 | mcf5206e }, -{"msacmw", two(0120220, 0001440), two(0170670, 0005460), "uNuoMhasRn", mcf5307 | mcf5206e }, -{"msacmw", two(0120230, 0001440), two(0170670, 0005460), "uNuoMh+sRn", mcf5307 | mcf5206e }, -{"msacmw", two(0120240, 0001440), two(0170670, 0005460), "uNuoMh-sRn", mcf5307 | mcf5206e }, -{"msacmw", two(0120250, 0001440), two(0170670, 0005460), "uNuoMhdsRn", mcf5307 | mcf5206e }, - -{"msacl", two(0120000, 0004400), two(0170660, 0005400), "RsRm", mcf5307 | mcf5206e }, -{"msacl", two(0120000, 0005400), two(0170660, 0005400), "RsRmMh", mcf5307 | mcf5206e }, -{"msacl", two(0120220, 0004400), two(0170670, 0005460), "R3R1asRn", mcf5307 | mcf5206e }, -{"msacl", two(0120230, 0004400), two(0170670, 0005460), "R3R1+sRn", mcf5307 | mcf5206e }, -{"msacl", two(0120240, 0004400), two(0170670, 0005460), "R3R1-sRn", mcf5307 | mcf5206e }, -{"msacl", two(0120250, 0004400), two(0170670, 0005460), "R3R1dsRn", mcf5307 | mcf5206e }, -{"msacl", two(0120220, 0005400), two(0170670, 0005460), "R3R1MhasRn", mcf5307 | mcf5206e }, -{"msacl", two(0120230, 0005400), two(0170670, 0005460), "R3R1Mh+sRn", mcf5307 | mcf5206e }, -{"msacl", two(0120240, 0005400), two(0170670, 0005460), "R3R1Mh-sRn", mcf5307 | mcf5206e }, -{"msacl", two(0120250, 0005400), two(0170670, 0005460), "R3R1MhdsRn", mcf5307 | mcf5206e }, -{"msacml", two(0120220, 0004440), two(0170670, 0005460), "R3R1asRn", mcf5307 | mcf5206e }, -{"msacml", two(0120230, 0004440), two(0170670, 0005460), "R3R1+sRn", mcf5307 | mcf5206e }, -{"msacml", two(0120240, 0004440), two(0170670, 0005460), "R3R1-sRn", mcf5307 | mcf5206e }, -{"msacml", two(0120250, 0004440), two(0170670, 0005460), "R3R1dsRn", mcf5307 | mcf5206e }, -{"msacml", two(0120220, 0005440), two(0170670, 0005460), "R3R1MhasRn", mcf5307 | mcf5206e }, -{"msacml", two(0120230, 0005440), two(0170670, 0005460), "R3R1Mh+sRn", mcf5307 | mcf5206e }, -{"msacml", two(0120240, 0005440), two(0170670, 0005460), "R3R1Mh-sRn", mcf5307 | mcf5206e }, -{"msacml", two(0120250, 0005440), two(0170670, 0005460), "R3R1MhdsRn", mcf5307 | mcf5206e }, +{"msacw", two(0120000, 0000400), two(0170660, 0005400), "uMum", mcfmac }, +{"msacw", two(0120000, 0001400), two(0170660, 0005400), "uMumMh", mcfmac }, +{"msacw", two(0120220, 0000400), two(0170670, 0005460), "uNuoasRn", mcfmac }, +{"msacw", two(0120230, 0000400), two(0170670, 0005460), "uNuo+sRn", mcfmac }, +{"msacw", two(0120240, 0000400), two(0170670, 0005460), "uNuo-sRn", mcfmac }, +{"msacw", two(0120250, 0000400), two(0170670, 0005460), "uNuodsRn", mcfmac }, +{"msacw", two(0120220, 0001400), two(0170670, 0005460), "uNuoMhasRn", mcfmac }, +{"msacw", two(0120230, 0001400), two(0170670, 0005460), "uNuoMh+sRn", mcfmac }, +{"msacw", two(0120240, 0001400), two(0170670, 0005460), "uNuoMh-sRn", mcfmac }, +{"msacw", two(0120250, 0001400), two(0170670, 0005460), "uNuoMhdsRn", mcfmac }, +{"msacmw", two(0120220, 0000440), two(0170670, 0005460), "uNuoasRn", mcfmac }, +{"msacmw", two(0120230, 0000440), two(0170670, 0005460), "uNuo+sRn", mcfmac }, +{"msacmw", two(0120240, 0000440), two(0170670, 0005460), "uNuo-sRn", mcfmac }, +{"msacmw", two(0120250, 0000440), two(0170670, 0005460), "uNuodsRn", mcfmac }, +{"msacmw", two(0120220, 0001440), two(0170670, 0005460), "uNuoMhasRn", mcfmac }, +{"msacmw", two(0120230, 0001440), two(0170670, 0005460), "uNuoMh+sRn", mcfmac }, +{"msacmw", two(0120240, 0001440), two(0170670, 0005460), "uNuoMh-sRn", mcfmac }, +{"msacmw", two(0120250, 0001440), two(0170670, 0005460), "uNuoMhdsRn", mcfmac }, + +{"msacl", two(0120000, 0004400), two(0170660, 0005400), "RsRm", mcfmac }, +{"msacl", two(0120000, 0005400), two(0170660, 0005400), "RsRmMh", mcfmac }, +{"msacl", two(0120220, 0004400), two(0170670, 0005460), "R3R1asRn", mcfmac }, +{"msacl", two(0120230, 0004400), two(0170670, 0005460), "R3R1+sRn", mcfmac }, +{"msacl", two(0120240, 0004400), two(0170670, 0005460), "R3R1-sRn", mcfmac }, +{"msacl", two(0120250, 0004400), two(0170670, 0005460), "R3R1dsRn", mcfmac }, +{"msacl", two(0120220, 0005400), two(0170670, 0005460), "R3R1MhasRn", mcfmac }, +{"msacl", two(0120230, 0005400), two(0170670, 0005460), "R3R1Mh+sRn", mcfmac }, +{"msacl", two(0120240, 0005400), two(0170670, 0005460), "R3R1Mh-sRn", mcfmac }, +{"msacl", two(0120250, 0005400), two(0170670, 0005460), "R3R1MhdsRn", mcfmac }, +{"msacml", two(0120220, 0004440), two(0170670, 0005460), "R3R1asRn", mcfmac }, +{"msacml", two(0120230, 0004440), two(0170670, 0005460), "R3R1+sRn", mcfmac }, +{"msacml", two(0120240, 0004440), two(0170670, 0005460), "R3R1-sRn", mcfmac }, +{"msacml", two(0120250, 0004440), two(0170670, 0005460), "R3R1dsRn", mcfmac }, +{"msacml", two(0120220, 0005440), two(0170670, 0005460), "R3R1MhasRn", mcfmac }, +{"msacml", two(0120230, 0005440), two(0170670, 0005460), "R3R1Mh+sRn", mcfmac }, +{"msacml", two(0120240, 0005440), two(0170670, 0005460), "R3R1Mh-sRn", mcfmac }, +{"msacml", two(0120250, 0005440), two(0170670, 0005460), "R3R1MhdsRn", mcfmac }, {"mulsw", one(0140700), one(0170700), ";wDd", m68000up|mcf }, {"mulsl", two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32 }, @@ -1716,9 +1714,9 @@ {"pvalid", two(0xf000, 0x2800), two(0xffc0, 0xffff), "Vs&s", m68851 }, {"pvalid", two(0xf000, 0x2c00), two(0xffc0, 0xfff8), "A3&s", m68851 }, - /* FIXME: don't allow Dw==Dx. */ -{"remsl", two(0x4c40, 0x0800), two(0xffc0, 0x8ff8), "vsD3D1", mcf5307 | mcf5206e }, -{"remul", two(0x4c40, 0x0000), two(0xffc0, 0x8ff8), "vsD3D1", mcf5307 | mcf5206e }, +/* FIXME: don't allow Dw==Dx. */ +{"remsl", two(0x4c40, 0x0800), two(0xffc0, 0x8ff8), "vsD3D1", mcfhwdiv }, +{"remul", two(0x4c40, 0x0000), two(0xffc0, 0x8ff8), "vsD3D1", mcfhwdiv }, {"reset", one(0047160), one(0177777), "", m68000up }, @@ -1935,6 +1933,8 @@ {"wddataw", one(0172100), one(0177700), "~s", mcf }, {"wddatal", one(0172200), one(0177700), "~s", mcf }, +{"wdebug", two(0175720, 03), two(0177770, 0xffff), "as", mcf }, +{"wdebug", two(0175750, 03), two(0177770, 0xffff), "ds", mcf }, }; const int m68k_numopcodes = sizeof m68k_opcodes / sizeof m68k_opcodes[0];