diff -Naur /hanishkvc/mirrors/uClinux/uClinux-2.4.x/arch/armnommu/config.in uClinux-2.4.x-hankvc/arch/armnommu/config.in
--- /hanishkvc/mirrors/uClinux/uClinux-2.4.x/arch/armnommu/config.in	Fri Sep 14 16:07:32 2001
+++ uClinux-2.4.x-hankvc/arch/armnommu/config.in	Fri Sep 14 16:45:11 2001
@@ -63,6 +63,8 @@
    define_bool CONFIG_CPU_26 n
    define_bool CONFIG_CPU_ARM940T y
    define_bool CONFIG_NO_PGT_CACHE y
+   define_bool CONFIG_CPU_WITH_CACHE y
+   define_bool CONFIG_CPU_WITH_MCR_INSTRUCTION y
 bool 'Set flash/sdram size and base addr' CONFIG_SET_MEM_PARAM
 
 if [ "$CONFIG_SET_MEM_PARAM" = "y" ]; then
@@ -93,6 +95,8 @@
    define_bool CONFIG_CPU_32 y
    define_bool CONFIG_CPU_26 n
    define_bool CONFIG_NO_PGT_CACHE y
+   define_bool CONFIG_CPU_WITH_CACHE y
+   define_bool CONFIG_CPU_WITH_MCR_INSTRUCTION y
    define_hex DRAM_BASE 0x08000000
    define_hex DRAM_SIZE 0x00200000
    define_hex FLASH_MEM_BASE 0x08400000
@@ -104,6 +108,8 @@
    define_bool CONFIG_NO_PGT_CACHE y
    define_bool CONFIG_CPU_ARM710 y
    define_bool CONFIG_CPU_32 y
+   define_bool CONFIG_CPU_WITH_CACHE y
+   define_bool CONFIG_CPU_WITH_MCR_INSTRUCTION n
    define_hex DRAM_BASE 0x01000000
    define_bool CONFIG_CPU_AT91X40 y
    define_hex DRAM_SIZE 0x00200000
diff -Naur /hanishkvc/mirrors/uClinux/uClinux-2.4.x/arch/armnommu/kernel/head-armv.S uClinux-2.4.x-hankvc/arch/armnommu/kernel/head-armv.S
--- /hanishkvc/mirrors/uClinux/uClinux-2.4.x/arch/armnommu/kernel/head-armv.S	Fri Sep 14 16:07:46 2001
+++ uClinux-2.4.x-hankvc/arch/armnommu/kernel/head-armv.S	Fri Sep 14 16:45:11 2001
@@ -213,10 +213,21 @@
 		.long	SYMBOL_NAME(init_task_union)+8192
 
 __ret:		ldr	lr, __switch_data
+#ifdef CONFIG_CPU_WITH_CACHE
+# ifdef CONFIG_CPU_WITH_MCR_INSTRUCTION
 		mcr	p15, 0, r0, c1, c0
 		mov	r0, r0
 		mov	r0, r0
 		mov	r0, r0
+# else
+#  warning 	"FIXME: Enable Cache, Other settings without MCR Instruction"
+		@ Note r0 is initialized suitably to enable Cache
+		@ and additional settings if any in proc_armX.S file
+		@ A possible code here
+		@ldr	r2, CACHE_CONTROL_MEM_LOCATION
+		@str	r0, [r2]
+# endif
+#endif
 		mov	pc, lr
 
 		/*
@@ -426,7 +437,14 @@
 		sub	r5, r5, r10			@ convert addresses
 		add	r7, r7, r5			@ to our address space
 		add	r10, r9, r5
+#ifdef CONFIG_CPU_WITH_MCR_INSTRUCTION
 		mrc	p15, 0, r9, c0, c0		@ get processor id
+#else
+# warning 	"FIXME: Get Processor ID without MCR Instruction"
+		@ A possible code
+		@ldr	r9, PROCESSOR_ID_MEM_LOCATION
+		@ldr	r9, [r9]
+#endif
 1:		ldmia	r10, {r5, r6, r8}		@ value, mask, mmuflags
 		and	r6, r6, r9			@ mask wanted bits
 		teq	r5, r6
diff -Naur /hanishkvc/mirrors/uClinux/uClinux-2.4.x/arch/armnommu/kernel/process.c uClinux-2.4.x-hankvc/arch/armnommu/kernel/process.c
--- /hanishkvc/mirrors/uClinux/uClinux-2.4.x/arch/armnommu/kernel/process.c	Fri Sep 14 16:08:01 2001
+++ uClinux-2.4.x-hankvc/arch/armnommu/kernel/process.c	Fri Sep 14 16:45:11 2001
@@ -183,16 +183,27 @@
 		processor_modes[processor_mode(regs)],
 		thumb_mode(regs) ? " (T)" : "",
 		get_fs() == get_ds() ? "kernel" : "user");
+/* We are interested only if we have cache related or CPU Control info */
 #if defined(CONFIG_CPU_32)
 	{
 		int ctrl, transbase, dac;
 		  __asm__ (
+#ifdef CONFIG_CPU_WITH_MCR_INSTRUCTION				  
 		"	mrc p15, 0, %0, c1, c0\n"
+#else
+# warning		"FIXME: Get CPU control info if any without MCR Instruction"
+		"	mov %0, #0 @ Dummy for now\n"
+#endif
+#ifndef NO_MM
 		"	mrc p15, 0, %1, c2, c0\n"
 		"	mrc p15, 0, %2, c3, c0\n"
 		: "=r" (ctrl), "=r" (transbase), "=r" (dac));
 		printk("Control: %04X  Table: %08X  DAC: %08X\n",
 		  	ctrl, transbase, dac);
+#else
+		: "=r" (ctrl));
+		printk("Control: %X\n", ctrl);
+#endif		
 	}
 #endif
 }
diff -Naur /hanishkvc/mirrors/uClinux/uClinux-2.4.x/arch/armnommu/mm/proc-arm6,7.S uClinux-2.4.x-hankvc/arch/armnommu/mm/proc-arm6,7.S
--- /hanishkvc/mirrors/uClinux/uClinux-2.4.x/arch/armnommu/mm/proc-arm6,7.S	Fri Sep 14 16:08:23 2001
+++ uClinux-2.4.x-hankvc/arch/armnommu/mm/proc-arm6,7.S	Fri Sep 14 16:45:11 2001
@@ -38,8 +38,12 @@
 ENTRY(cpu_arm6_dcache_invalidate_range)
 ENTRY(cpu_arm7_dcache_invalidate_range)
 		mov	r0, #0
-#ifndef NO_MM        
+#ifdef (CONFIG_CPU_WITH_CACHE) 
+# ifdef (CONFIG_CPU_WITH_MCR_INSTRUCTION)
 		mcr	p15, 0, r0, c7, c0, 0		@ flush cache
+# else
+#  warning		"FIXME: Flush cache without MCR Instruction"
+# endif
 #endif        
 ENTRY(cpu_arm6_dcache_clean_page)
 ENTRY(cpu_arm7_dcache_clean_page)
@@ -142,7 +146,7 @@
 		orr	r1, r2, #1			@ simulate FSR
 		mov	r0, #0				@ gotta have something...
 #else        
-    mrc	p15, 0, r0, c6, c0, 0		@ get FAR
+		mrc	p15, 0, r0, c6, c0, 0		@ get FAR
 		mrc	p15, 0, r3, c5, c0, 0		@ get FSR
 #endif        
 		and	r3, r3, #255
@@ -269,9 +273,18 @@
 ENTRY(cpu_arm7_proc_fin)
 		mov	r0, #F_BIT | I_BIT | SVC_MODE
 		msr	cpsr_c, r0
-		mov	r0, #0x31			@ ....S..DP...M
 #ifndef	NO_MM
+		mov	r0, #0x31			@ ....S..DP...M
 		mcr	p15, 0, r0, c1, c0, 0		@ disable caches
+#else
+# ifdef CONFIG_CPU_WITH_CACHE
+#  ifdef CONFIG_CPU_WITH_MCR_INSTRUCTION
+		mov	r0, #0x30			@ .......DP....
+		mcr	p15, 0, r0, c1, c0, 0		@ disable caches
+#  else
+#   warning	"FIXME: Disable cache without MCR Instruction"
+#  endif
+# endif
 #endif        
 		mov	pc, lr
 
@@ -289,8 +302,14 @@
 ENTRY(cpu_arm6_set_pgd)
 ENTRY(cpu_arm7_set_pgd)
 		mov	r1, #0
-#ifndef	NO_MM       
+#ifdef CONFIG_CPU_WITH_CACHE
+# ifdef CONFIG_CPU_WITH_MCR_INSTRUCTION
 		mcr	p15, 0, r1, c7, c0, 0		@ flush cache
+# else
+#  warning		"FIXME: Flush cache without MCR Instruction"
+# endif
+#endif
+#ifndef	NO_MM       
 		mcr	p15, 0, r0, c2, c0, 0		@ update page table ptr
 		mcr	p15, 0, r1, c5, c0, 0		@ flush TLBs
 #endif        
@@ -364,8 +383,16 @@
 ENTRY(cpu_arm6_reset)
 ENTRY(cpu_arm7_reset)
 		mov	r1, #0
-#ifndef	NO_MM        
+#ifdef CONFIG_CPU_WITH_CACHE
+# ifdef CONFIG_CPU_WITH_MCR_INSTRUCTION
 		mcr	p15, 0, r1, c7, c0, 0		@ flush cache
+		mov	r1, #0x30
+		mcr	p15, 0, r1, c1, c0, 0		@ turn off Cache etc
+# else
+#  warning		"FIXME: Flush and Disable cache without MCR Instruction"
+# endif
+#endif
+#ifndef	NO_MM        
 		mcr	p15, 0, r1, c5, c0, 0		@ flush TLB
 		mov	r1, #0x30
 		mcr	p15, 0, r1, c1, c0, 0		@ turn off MMU etc
@@ -391,27 +418,67 @@
 __arm6_setup:	mov	r0, #F_BIT | I_BIT | SVC_MODE
 		msr	cpsr_c, r0
 		mov	r0, #0
+#ifdef CONFIG_CPU_WITH_CACHE
+# ifdef CONFIG_CPU_WITH_MCR_INSTRUCTION
 		mcr	p15, 0, r0, c7, c0		@ flush caches on v3
+# else
+#  warning		"FIXME: Flush cache without MCR Instruction"
+		@ldr	r2, CACHE_CONTROL_MEM_LOCATION
+		@str	r0, [r2]
+# endif
+#endif
+#ifndef NO_MM
 		mcr	p15, 0, r0, c5, c0		@ flush TLBs on v3
 		mcr	p15, 0, r4, c2, c0		@ load page table pointer
 		mov	r0, #0x1f			@ Domains 0, 1 = client
 		mcr	p15, 0, r0, c3, c0		@ load domain access register
 		mov	r0, #0x3d			@ ....S..DPWC.M
 		orr	r0, r0, #0x100
+#endif
+#ifdef CONFIG_CPU_WITH_CACHE
+# ifdef CONFIG_CPU_WITH_MCR_INSTRUCTION
+		mov	r0, #0x3c			@ .......DPWC..
+# else 
+#  warning		"FIXME: Enable Cache and Others without MCR Instruction"
+# endif
+#else
+		@ Just in case r0 is modified by any code above			
+		mov	r0, #0x0			
+# warning		"FIXME: Setup anything if required"
+#endif
 		mov	pc, lr
 
 __arm7_setup:	mov	r0, #F_BIT | I_BIT | SVC_MODE
 		msr	cpsr_c, r0
 		mov	r0, #0
-#ifndef	NO_MM        
+#ifdef CONFIG_CPU_WITH_CACHE
+# ifdef CONFIG_CPU_WITH_MCR_INSTRUCTION
 		mcr	p15, 0, r0, c7, c0		@ flush caches on v3
+# else
+#  warning		"FIXME: Flush cache without MCR Instruction"
+		@ldr	r2, CACHE_CONTROL_MEM_LOCATION
+		@str	r0, [r2]
+# endif
+#endif
+#ifndef	NO_MM        
 		mcr	p15, 0, r0, c5, c0		@ flush TLBs on v3
 		mcr	p15, 0, r4, c2, c0		@ load page table pointer
 		mov	r0, #0x1f			@ Domains 0, 1 = client
 		mcr	p15, 0, r0, c3, c0		@ load domain access register
-#endif        
 		mov	r0, #0x7d			@ ....S.LDPWC.M
 		orr	r0, r0, #0x100
+#endif
+#ifdef CONFIG_CPU_WITH_CACHE
+# ifdef CONFIG_CPU_WITH_MCR_INSTRUCTION
+		mov	r0, #0x7c			@ ......LDPWC..
+# else 
+#  warning		"FIXME: Enable Cache and Others without MCR Instruction"
+# endif
+#else
+		@ Just in case r0 is modified by any code above			
+		mov	r0, #0x0			
+# warning		"FIXME: Setup anything if required"
+#endif
 		mov	pc, lr
 
 /*